Operating conditions such as temperature, aging, radiations can introduce faults and generate errors in electronic devices. The rad-hard technologies are used as a protection against faults but their cost is prohibitive. CEA-LIST and the laboratory Lab-STICC from the University of South Brittany propose an alternative approach which operates at the architectural and software level. It relies on an innovative method to map applications on Coarse-Grained Reconfigurable Architecture. In this context, the Ph.D. student will have to explore memory organization and data access management of the architecture, taking into account the power consumption constraint and fault tolerance. The Ph.D. student will also have to study the impact on the network communication. The hardware design choices will be formalized to fit with the application mapping technology developed in partnership with Lab-STICC.

This position is open until it is filled.

Département: DM2I (LIST)
Laboratory: Laboratoire Capteurs et Architectures Electroniques
Start Date: 01-10-2015
ECA Code: SL-DRT-15-0993
Contact: gwenole.corre<στο>cea.fr