The context of the thesis concerns the main topics of micro-nanoelectronics and the understanding of the physics involved in nano-transistors beyond 7nm node. This means to study devices with gate length below 10nm with three main challenges:

-Electrostatic control of CMOS transistors which determines the static and dynamic power consumption

-Performance related to the tradeoff between ON state current and parasitic capacitances

-Variability control for logic

These studies are supported by a CEA transverse program (ZeroPOVA) between basic research and applied reseach.

The targeted devices are trigate transitors with channel materials designed for their band structures properties (tunnel junctions, heterostructured channels, semi-metal…)

The first task is to provide a benchmark of the technological approaches with focus on fabrication/process, device performance and design interest.

Once a promising architecture will be defined, an in-depth analysis of the required process modules will be conducted (narrow channel patterning, SiGe for channel and S/D, junctions optimization, …). Then a complete integration will performed (Leti clean rooms)

In parallel a strong connection with design teams will enable to define compact models in order to evaluate innovative circuits based on this architecture.

This position is open until it is filled.

Department: Département Composants Silicium (LETI)
Laboratory: Laboratoire Dispositifs Innovants
Start Date: 01-03-2015
ECA Code: SL-DRT-15-0816
Contact: cyrille.leroyer<στο>cea.fr