The purpose of the thesis is to prepare the next generation of OR solvers. We will study the hardware acceleration possibility based on FPGA to run some or all of the OR algorithm. The blocks for which such a solution is not effective can be parallelized and executed on a standard computing platform. Thus, the proposed runtime correspond to a standard computing platform integrating FPGA. To access to this platform we require a set of tools. These tools should provide features such as (a) analysis and pre-compiling an input or problem or sub-problem of OR, (b) HW / SW partitioning and dedicated logic optimization and finally (c) generating an software executable and a bitstream.

The first step will be to find OR algorithms that are well suited for hardware acceleration. We then propose a HW / SW partitioning methodologies for different classes of algorithms.

The results will be implemented to lead to a compilation prototype starting from an OR instance and generating a software executable and a bitstream. Theses results will be implemented and executed on a computing platform integrating FPGA to evaluate the performance gain and the impact on the energy consumption of the proposed solution.

This position is open until it is filled.

Department: Département Architectures Conception et Logiciels Embarqués (LIST-LETI)
Laboratory: Laboratoires des fondements des systèmes Temps réel Embarqués
Start Date: 01-10-2015
ECA Code: SL-DRT-15-0335
Contact: kods.trabelsi<στο>cea.fr