This study aims at improving the performances of synchronization primitives (barriers, distributed mutexes, etc.) in multicore integrated circuits, by offering architectural improvements for transport of synchronization messages, and hardware/software accelerators for the most performance-constrained primitives.

Synchronization primitives indeed are a significant performance bottleneck in multicore systems. They are usually carried out through point-to-point exchanges of synchronization messages, controlled by the OS, which signal pending and occurred events (e.g. spinlock release or process waiting for a barrier). The delays introduced by these messages are all the longer as involved computing cores are numerous, which justifies the need of specific architectural features.

The proposed research work aims at elaborating and implementing evolution of multicore architectures to accelerate transfers of synchronization messages (e.g. dedicated “service interconnect”, multicast messages…). Besides, a study of real-life applications, representative of Cloud computing or HPC, will help identify the most performance-impacting synchronization primitives as candidates for joint hardware/software optimization.

Works will take place in digital architectures lab of CEA-Leti, in collaboration with embedded software lab. These teams gather the relevant hardware (architectures, IP blocks) and software (OS, modeling) skills to fulfill this study. They also offer advanced prototypes of multicore chips and hardware emulation tools, enabling real-life experimentation of designed solutions.

Required background: multicore architectures, VHDL & C programming languages, EDA tools, notions on OSs.

This position is open until it is filled.

Department: Département Architectures Conception et Logiciels Embarqués (LIST-LETI)
Laboratory: Laboratoire Intégration Silicium des Architectures Numériques
Start Date: 01-09-2015
ECA Code: SL-DRT-15-0005
Contact: jerome.martin<στο>cea.fr