Continued performance scaling of silicon MOS transistors meets immense challenges at sub-10 nm. Therefore, scaling-free technologies are now strongly needed to achieve further improvement of CMOS devices. A number of non-silicon channel materials have been considered for advanced CMOS devices such as SiGe or Ge (PMOS) as well as various III-V materials combinations including InGaAs, GaAs, InAs (NMOS). The co-integration of Ge/III-V channels on silicon substrates is expected to give promising device structures for high-performance CMOS future generations. In this context, the control of SiGe, Ge and III-V alloys ?surface preparation? steps stands out as a key point for integration. Of the capacity to effectively remove all the surface contaminants and to check the surface functionalization of these various types of materials will depend directly their possibilities of industrial integrations. In this context, this PhD work will focus on i)measuring and explaining materials fundamental behavior in liquid solutions; ii) surface functionalization evaluation; iii) surface preparation impact on physic-chemical, morphological and electric properties of epitaxial layers (for the Source and Drain re-growth), or deposited layers (gate stack dielectric, metal for the metallic contact); iv)surface preparation sequences integration on functional MOS devices.

This position is open until it is filled.

Département: Département Technologies Silicium (LETI)
Laboratory: Laboratoire
Start Date: 01-09-2015
ECA Code: SL-DRT-15-1002
Contact: virginie.loup<στο>cea.fr