PhD Position – Integrated network routing system base of ternary resistive associative memory

The proposed research work consists in the design and realization of a comprehensive solution for network packet routing, based on the resistive memory technologies developed at LETI. The new architecture will require innovating and optimized solutions for data pre indexing and non-blocking update, around the original ternary associative memory component. Special attention will be given to variability compensation and energy efficiency. The increase of internet traffic has dramatically raised the computing power needed from packet routing. The capacity and density of CMOS ternary associative memory (TCAM) is a critical limiting factor for current solutions. Moreover, network routing has additional specificities which require to trade latency against hardware complexity and energy efficiency. Resistive memory is a promising technology for the realization of high capacity TCAMs. Among them, The ReRam technology offers a 4x to 20x increase in density, and is compatible with standard CMOS process. However, the intrinsic variability and the constraints due to the electro-forming of its devices complicate the design of the elementary cells, of the memory array as well as the periphery circuitry. The candidate will rely on LETI technology to elaborate a ternary associative memory component, including variability compensation mechanisms. He will also complement the component with specific logical functions such as pre-indexing and support of transparent update. The study will take place within the micro-electronic design laboratory at LETI, in close collaboration with the RRAM technology development team. The design of the memory component will be done using current CAD tools, and the logical design will use HDL (VHDL or Verilog). Demonstrators will be implemented on silicon and tested.

This position is open until it is filled.

Département: Département Architectures Conception et Logiciels Embarqués (LIST-LETI)
Laboratory: Laboratoire Intégration Silicium des Architectures Numériques
Start Date: 01-05-2015
ECA Code: SL-DRT-15-0408
Contact: yves.durand<στο>cea.fr